What is the maximum distance of the I2C bus?

This depends on the load of the bus and the speed you run at. In typical applications, the length is a few meters (9-12ft). The maximum capacitive load has been specified (see also the electrical Spec's in the I2C FAQ). Another thing to be taken into account is the amount of noise picked up by long cabling. This noise can disturb the signal transmitted over the bus so badly that it becomes unreadable.

The length can be increased significantly by running at a lower clock frequency. One particular application - clocked at about 500Hz - had a bus length of about 100m (300ft). If you are careful in routing your PCB's and use proper cabling (twisted pair and/or shielded cable), you can also gain some length.

If you need to go far at high speed, you can use an active current source instead of a simple pull-up resistor. Philips has a standalone product for this purpose. Using a charge pump also reduces "ghost signals" caused by reflections at the end of the bus lines.

I'd like to extend the I2C bus. Is there something like a repeater for I2C?

Yes indeed this exists. Philips manufactures a special chip to buffer the bi-directional lines of the I2C bus. Typically, this is a current amplifier. It  forces current into the wiring (a couple of mA). That way you can overcome the capacitance of long wiring.

However, you will need this component on both sides of the line. The charge pump in this devices can deliver currents up to 30mA which is way too much for a normal I2C chip to handle. With these buffers you can handle loads up to 2nF. The charge amplifier 'transforms' this load down to a 200pF load which is still acceptable by I2C components.

Can I do galvanic decoupling of my I2C bus?

This is possible. The circuit is rather complex due to the bi-directional nature of the I2C bus.

The following figure shows a possible solution:

Galvanic decoupling

Component Values:

Note: Since the speed of the I2C bus can be rather high, it is recommended to use a fast optocoupler. However, this circuit will not work on speeds higher then 10KHz. A 6N139 will do the job in all cases. The two PNP and the two NPN transistors can be any standard type, e.g. 2N2219 and 2N2222 (USA) or BC547 and BC557 (EUROPE).

How does it work ?

The problem with bi-directional lines is that a buffer tends to get stuck on a certain level. This case has been taken into account in the above schematic. In the following explanation we assume that the left side is transmitting and the right side is receiving (the circuit is symmetrical)

Let's assume we send a logic 1 into the left side. The LED of the top optocoupler will stay dark. Since its transistor does not receive any light, it is not turned on. The next transistor does not get driven and the line at the end is being pulled high via resistors 1' and 3'. The PNP transistor 5' will not get driven. Therefore the LED connected to it will not light up and there is no feedback signal.

Now let's see what will happen if we send a logic 0. The first transistor 5 will be turned on, therefore the led connected to it will start emitting light. This results in the fact that its matching transistor will turn on. The transistor connected to the emitter will be turned on also. The output line is now being pulled low via resistor 3'. This low level would turn on the PNP transistor, which would result in the other optocoupler to light, its transistor to turn on etc. In other words, the circuit would go into a lock-up. However, since the NPN transistor is pulling the anode of the LED to ground, this will not happen. This way we have eliminated the deadlock.

Are there stand-alone I2C controllers?

Yes indeed. There is a special chip to do the I2C interfacing. The PCD8584 or PCF8584 incorporate a complete I2C interface. These chips are designed in such way that they can interface to almost any microcontroller around.

How can I generate a repeated start condition?

Let's assume the following situation: The controller lets the SCL line go high and the device pulls SDA low to acknowledge. So far no problem but how do you generate a repeated start condition now? The device is pulling SDA low.

First you have to complete the ACK cycle. To do this, you must pull SCL low again. The slave will release the data line when it detects that SCL is low. Now you can issue a stop command. To do this, you let the SCL go high again and then pull low the SDA line.

This is the confusing part of the procedure. Normally, you would suspect that by letting the clock line go high again you will be clocking in the first bit of a new byte. As a matter of fact that is the case. But since the chip will detect a START condition, this operation gets cancelled.

Can I abort an ongoing I2C bus transmission?

Is it okay to abort an on-going transmission any time.

According to the specification, this should work. It depends on the layout of the component. A real I2C compatible IC will be able to handle this. It might make sense to test this before you use it.

Usually, when a START or STOP condition is detected, the internal logic of the chip is forced into a certain state. Internally, the logic that detects START and STOP is different from the logic that does all other processing. The START together with the address register is to be considered as a functional unit inside the chip.

When a START is detected, all internal operations are cancelled and the chip will compare the incoming data with its own address.

When a STOP is detected, ALL chips on the bus will reset their internal logic to IDLE mode except for the START detector (this is also used to cut power consumption). Therefore, when a start condition is issued on the bus, the START detector will 'wake-up' the rest of the internal logic.

Do I need to generate an ACK in read mode on the last byte?

This is a somewhat puzzling question. Indeed this is a bit strange. Usually, if you have read the last byte in a chip and generate an ACK, the chip should do nothing anymore, so the bus should be clear for you to create a STOP condition. Apparently, there are some chips that start transmitting data again. One such chip is the PCF 8574 I/O expander.

Though not always desirable, this feature can come in handy. If you need to sample incoming data fast, then you just continue reading from the chip. This prevents that you lose 'arbitration' of the bus in a multi-master environment.

It also speeds things up. You don't have to address the chip over and over again so you save the time for START, Address, ACK and STOP stage for every next byte read. This can lead to a more than doubled transfer rate.

Why does the SCL line have to be bi-directional?

The clock line needs to be bi-directional when using a MULTI-MASTER protocol and when using the synchronization protocol.

When you are using only one Master then this is not required since the clock will always be generated by this device. If you run Multi-master then this changes. One master must be able to receive data from another master. At that time it must be able to receive clock information via the clock line also.

How can I implement an active pull-up resistor to enhance the bus length?

You can use an IC or build it with discrete components. All you will need is some resistors and an off-the-shelf analog switch. Here comes the schematic:

Schematic diagram

How it works:

Rs are serial resistors used to minimize cross talk and undershoot. They also protect the I/O drivers of the I2C devices against higher than allowed voltages and current injection. These resistors are advised if you run a long bus on high speed (such as in enhanced I2C mode).

When the bus becomes idle, all output stages on the bus are turned off and SCL and SDA) go high. This will not happen immediately, the voltage will rather rise during a certain time. Now assume the switch (IC1) is not there. The charge time of the bus capacitor would only be determined by the value of R1. The larger R1 and Rs, the longer it will take for the bus to reach a sufficient stable HIGH level.

We can't make the Rs resistors too small because then we would go out of spec on the maximum allowable current into one I2C device when turning on its output driver.

When we calculate for a current of 3mA, we end up at approximately 1800 Ohms for the serial resistance.

      5V / 3mA = 1666 Ohms.

To stay somewhere below this 3mA rating, we pick 1800 Ohms. The charge time for a bus capacitance of about 200pF would be around 360 ns. That is out of spec. The spec for rise or fall time in Fast I2C is set to approx 300ns.

But we can't drop the value of our resistor without breaking the other spec of 3mA of maximum current.

The idea is to change the value of the resistor temporarily using the analog switch IC1. If the voltage level sensed by the switch is in the range 0.8 to 2 volts then it will turn on. This means that as soon as the voltage on the SDA line starts rising, resistor R2 will kick in. R1 and R2 in parallel result in a resistance of 720 Ohms. This increases the charge current to a value of

5 volts / 720 Ohms = 7 mA.

This is allowable for a brief period of time. Of course all of this is a dynamic process. The actual charge current will change due to the fact that the bus voltage will rise.

A small graphical representation will explain more:


Waveform 1 represents turning off the I2C device, which will release the bus lines so that they can go HIGH.

Waveform 2 is what you get if you only use a resistor. The bus slowly comes up to 5 volts due to RC constant of the pull-up resistor R1 and the parasitic capacitance of the bus line Cp.

Waveform 3 shows the analog switch kicking in. If the bus line is at approx 0.7 volts it closes. It opens again when the bus reaches approx 3 volts.

Waveform 4 is how the voltage on the bus changes. You can see that it rises much faster when the switch is turned on.

Finally, waveform 5 shows the current flowing into the I2C device. It starts at approx 3mA.

When the output stage is turned off, this current slightly drops due to the fact that the voltage on the bus is rising. The moment our switch kicks in you see the current doubling. The same effect is then present as before the switch closed: the current drops as the bus voltage rises. When the switch opens again the current drops a little to charge the capacitor up to 5 volts. But at that time, all chips already detect a logic one and are well within the 300ns rise time.

How can I monitor the I2C bus?

There are a few commercial I2C monitor / debuggers around that can do this.

There is another possibility to do this: By using the stand-alone I2C controller PCF8584 from Philips. This chip has a certain mode in which it does not take part in the real I2C action but only records what is going on. It listens to all addresses, but does not generate any acknowledge. Using some software routines and a MCU you could build a universal I2C data logger.

How can I test / debug the I2C bus?

There is no general way to debug an I2C bus. However, a few guidelines might help to get it running.

First thing is to check the levels on the bus. You should see a clear signal that has a low level that is lower then 0.8 volt and a high level which is at least 3.5 volts.

If the high level is not high enough or does not rise fast enough then you can try to lower the value of the pull up resistor. You must take care however not to surpass the maximum allowable current in the I2C driver stage. The minimum allowable resistor for a 5 volt driven I2C bus is 5 V / 3mA = 1600 Ohms. A typical value of 4700 ohm should work fine.

Make sure the bus is not 'stuck' to '0'. This could be the result of a bad power supply (chips go into latch up during power-on) or a bad chip.

There are a few commercial I2C monitor / debuggers around.

Is there an RS232 / I2C converter?

Yes, there are at least two of them. Please visit one of the following links:

Which microcontrollers do have an on-chip I2C interface?

A LOT of MCU's have a real I2C interface implemented in hardware, but this should not restrict the use of the I2C bus on other MCU's. ANY MCU can be made to talk to I2C using some small software routines.

There are microcontrollers with on-chip I2C modules as well as stand-alone I2C bus peripherals.

To list all the devices here would be impossible. A good overview can be found here: http://www.embeddedlinks.com/chipdir (search for keyword I2C)

Are there PC cards available with an I2C interface?

There are a number of debugging tools out there which can monitor an I2C bus

How can I use my oscilloscope to trigger on an I2C start condition?

Everybody who ever tried to make a simple oscilloscope Sync on I2C signals knows that this is almost impossible. You will need a very advanced (read: very expensive) scope or logic analyzer to monitor I2C signals. You can do it if your scope has the possibility to trigger on 2 independent channels and if you can program the conditions like level, high-to-low or low-to-high. One such a scope is a Tektronix TDS540.

Here is a little piece of hardware which can help us out.

Schematic diagram

How it works:

The Start condition in I2C is defined as: Pulling the SDA line low while SCL line is high - which is exactly what the little circuit monitors.

Every transition of the SDA line from HIGH to LOW will make the D-latch sample the level of the SCL line. If at that time the SCL line is low, then the output of the D-latch will go or remain low.

On the other hand, if the SCL line is HIGH (which indicates a start condition), the output of the D-latch will become high.

If you connect the output of the D-latch to the trigger input of a common oscilloscope and set the scope to trigger on RISING edge of the trigger channel, then you have exactly what you want. Every time a start condition is transmitted on the bus, the D-latch will trigger the scope.

What bus speeds are available with I2C?

The bus speed for I2C was increased over the years. The following modes are available: