8051 Memory Configuartions with C Compilers

by Andy Ayre, ESAcademy
based on the C51Primer, by Mike Beach, Hitex UK

The Keil and Raisonance C Compilers provide a variety of memory models. When do we choose which model?

[ Introduction | Available memory models | Choosing a model | Using a model ]

Physical Location Of The Memory Spaces

Perhaps the most initially confusing thing about the 8051 is that there are three different memory spaces, all of which start at the same address.

Other microcontrollers, such as the 68HC11, have a single Von Neuman memory configuration, where memory areas are located at sequential addresses; regardless of in what device they physically exist.

Within the 8051 CPU there is one such memory, the DATA on-chip RAM. This starts at D:00H (the 'D:' prefix implies DATA segment) and ends at D:7fH (127 decimal). This RAM can be used for program variables. It is directly addressable, so that instructions like 'MOV A,x' are usable. Above 80H the special function registers are located, which are again directly addressable. However, a second memory area exists between 80H and 0FFH which is only indirectly addressable and is prefixed by I: and known as IDATA. It is only accessible via indirect addressing (MOV A,@Ri) and effectively overlays the directly addressable SFR area. This constitutes an extended on-chip RAM area and was added to the ordinary 8051 design when the 8052 appeared. As it is only indirectly addressable, it is best left for stack use, which is, by definition, always indirectly addressed via the stack pointer SP. Just to confuse things, the normal directly addressable RAM from D:00H-D:80H can also be indirectly addressed by the MOV A,@Ri instruction!

Fig.1. - The 8051's Memory Spaces.

A third memory space, the CODE segment, also starts at zero, but this is reserved for the program. It typically runs from C:0000H to C:0FFFFH (65536 bytes) but as it is held within an external Flash, it can be any size up to 64KB (65536 bytes). The CODE segment is accessed via the program counter (PC) for opcode fetches and by DPTR for data. Obviously, being ROM, only constants can be stored here.

A fourth memory area is also off-chip, starting at X:0000H. This exists in an external RAM device and, like the C:0000H segment, can extend up to X:0FFFFH (65536 bytes). The 'X:' prefix implies the external XDATA segment (sometimes also referred to as XRAM). The 8051's only 16-bit register, the DPTR (data pointer) is used to access the XDATA. Finally, 256 bytes of XDATA can also be addressed in a paged mode. Here an 8-bit register (R0) is used to access this area, termed PDATA.

The obvious question is: "How does the 8051 prevent an access to C:0000H resulting in data being fetched from D:00H?"

The answer is in the 8051 hardware: When the CPU intends to access D:00H, the on-chip RAM is enabled by a purely internal READ signal - the external /RD pin is unchanged.

MOV A,40 ; Put value held in location 40 into the accumulator.

This addressing mode (direct) is the basis of the SMALL memory model.

MOV R0,#0A0H ; Put the value held in IDATA location 0A0H into
MOV A,@R0    ; the accumulator

This addressing mode is used to access the indirectly addressable on-chip memory above 80H and as an alternative way to get at the direct memory below this address.

A variation on DATA is BDATA (bit data). This is a 16 byte (128 bit) area, starting at 020H in the direct segment. It is useful in that it can be both accessed byte-wise by the normal MOV instructions and addressed by special bit-orientated instructions, as shown below:

SETB 20.0 ;
CLRB 20.0 ;

The external ROM device (C:0000H) is not enabled during RAM access. In fact, the external ROM is only enabled when a pin on the 8051 named the PSEN (program store enable) is pulled low. The name indicates that the main function of the ROM is to hold the program that is executed on the CPU.

The XDATA RAM and CODE ROM do not clash, as the XDATA device is only active during a request from the 8051 pins named READ or WRITE, whereas the CODE device only responds when the PSEN pin is low.

To help access the external XDATA RAM, special instructions exist, conveniently containing an 'X'...

MOV DPTR,#08000H
MOVX A,@DPTR ; "Put a value in A located at address in the external RAM, contained in the DPTR register (8000H)".

The above addressing mode forms the basis of the LARGE model.

MOVX R0,#080H ;
MOVX A,@R0 ;

This alternative access mode to external RAM forms the basis of the COMPACT memory model. Note that if Port 2 is attached to the upper address lines of the RAM, it can act like a manually operated "paging" control.

The important point to remember is that the PSEN pin is active when instructions are being fetched; READ and WRITE are active when MOVX.... ("move external") instructions are being carried-out.

Note that the 'X' means that the address is not within the 8051 but is contained in an external device, enabled by the READ and WRITE pins.

[ Introduction | Available memory models | Choosing a model | Using a model ]