I2C Bus Hardware
As explained earlier, the bus physically consists of 2 active wires called SDA (data) and SCL (clock), and a ground connection.
Both SDA and SCL are initially bi-directional. This means that in a particular device, these lines can be driven by the IC itself or from an external device. In order to achieve this functionality, these signals use open collector or open drain outputs (depending on the technology).
The bus interface is built around an input buffer and an open drain or open collector transistor. When the bus is IDLE, the bus lines are in the logic HIGH state (note that external pull-up resistors are necessary for this which is easily forgotten). To put a signal on the bus, the chip drives its output transistor, thus pulling the bus to a LOW level. The "pull-up resistor" in the devices as seen in the figure is actually a small current source or even non-existent.
The nice thing about this concept is that it has a "built-in" bus mastering technique. If the bus is "occupied" by a chip that is sending a 0, then all other chips lose their right to access the bus. More will be explained about this in the section about bus arbitration.
However, the open-collector technique has a drawback, too. If you have a long bus, this will have a serious effect on the speed you can obtain. Long lines present a capacitive load for the output drivers. Since the pull-up is passive, you are facing an RC constant which will reflect on the shapes of the signals. The higher this RC constant, the slower you can go. This is due to the effect that it influences the slew rate of the edges on the I2C bus. At a certain point, the ICs will not be able to distinguish clearly between a logic 1 and 0.
What's more is that you can get reflections at high speed. This can be so bad that "ghost signals" disturb your transmission and corrupt the data you transmit. Not even Schmitt triggers at the IC's inputs will be able to eliminate this effect.
Therefore some strict electrical specifications have been put together.
To overcome this problem, Philips has developed an active I2C terminator. This device consists of a twin charge pump and you can look at it as a dynamic resistor. The moment the state changes, it provides a large current (low dynamic resistance) to the bus. In doing so it can charge the parasitic capacitor very quickly. Once the voltage has risen above a certain level, the high current mode cuts out and the output current drops sharply.
Take a look at the following figure. As long as the bus is kept low (transistor C is on), the charge pump is disabled because the gate of transistor B is kept low by transistor A.
As soon as the chip releases the bus (A and C turn off), the capacitor will start charging, drawing current trough all four of the resistors (1 - 4). The voltage drop over resistor 2 will cause the transistor B to turn on, shorting out resistor 3. Since resistor 3 is a relatively low value, the current will rise. At a certain point in time, the drop between transistor B's gate and source will not be big enough to keep it switched on. It will then switch off and the charge injection will stop. At that time, only the external pull-up resistor remains to overcome the charge leakage on the bus.
Please note that this is a simple explanation. The actual device implements more circuitry, e.g. to prevent "overcharging" if another chip is still pulling the bus low.
This device can come in handy if you need to overcome several meters of I2C bus length.