166 Primer

An Introduction To The SAB80C166 Family

Version x2.00

This guide is intended to answer the typical questions on the SAB80C166 family that arise during CPU selection exercises and when the device is first used.

Points covered range from basic hardware design and pin allocation to C programming and debugging possibilities.

HTML version by Olaf 'Olu' Pfeiffer, Hitex

(C) Copyright Hitex (UK) Ltd. 1995

Contents

• SAB80C166 - RISC for Embedded Applications
• Introduction
• Conventional CISC Bottle-necks
• The RISC Architecture For Embedded Control
• Bus Interface
• Pipeline Side-Effects
• RISC Interrupt Response
• Registers And Multi-Tasking
• Coping With RISC Instruction Set Omissions
• RISC And Real World Peripherals
• RISC Benefits In Embedded Applications
• Basic SAB80C166 System Planning Considerations
• Clock Speeds
• Bus Modes
• Setting The Bus Mode
• Memory Map Recommendations
• CPU Throughput And Bus Mode
• Implications Of Bus Mode/Trading Port Pins For IO
• Allocating Pins/Port Pins In Your Application
• Port 0
• Port 1
• Port 2
• Port 3
• Port 4
• Port 5
• Port 6
• Port 7
• Port 8
• Interrupt Performance
• Conventional Interrupt Servicing Factors
• Software Interrupts
• Hardware Traps
• 80C166 Stacks
• Interrupt Structure
• Power Consumption
• The ICEconnect Emulation Interface
• The Problem
• The Solution -ICEconnect166
• Appendices
• Appendix A
• Appendix B
• Appendix C
• Appendix D